The present invention concerns dynamic memory control devices and, more particularly, a dynamic memory controller for use with single-chip microprocessors.
A single-chip microprocessor, having a central processing unit (CPU) and program-storing read-only memory (ROM) in addition to some amount of random-addressable memory (RAM), has been used for many applications. However, the amount of memory, whether of ROM or RAM type, contained in a typical single-chip microprocessor is often insufficient for the task to be handled. It is therefore often necessary to add additional external memory, particularly of the RAM type, which can at least temporarily store additional data for, and under the control of, the associated microprocessor. While static external memory is useable, it is often desired to use dynamic memory external to the single-chip microprocessor. The dynamic memory integrated circuits currently available are among the least expensive types of memory in use at this time, allowing overall system costs to be reduced by their use. Dynamic memory integrated circuits also consume less power than static memory devices, and thus reduce the cost of associated power supplies and cooling equipment. However, dynamic memories, which store charge in each internal memory cell as representative of the data element stored therein, require that the cell charge, which itself decays over time, be periodically refreshed to maintain the proper data state. This refresh operation is relatively critical in both the timing and the event sequencing requirements thereof. Further, when dynamic RAM memories are interfaced to microprocessor-based systems, additional system problems concerning connection of the microprocessor to the memory subsystem and reliable data transfer between the memory-subsystem and the microprocessor must be considered, in addition to the proper refresh operation.
It is known that a custom refresh controller can be provided by interconnection of a relatively large number of discrete logic devices. It is also known that a custom refresh controller can be implemented in large scale integration (LSI)circuit form, to provide a single integrated circuit package design. Such LSI packages are commercially available, as in the Intel 8202 or 8203 dynamic memory controller. However, these controllers are not adaptable for use with single-chip microcomputer designs. Further, even if these custom refresh controllers could be adapted to such a design, the cost of a dedicated memory controller is relatively expensive, as the controllers are relatively complex devices, and in some cases the custom controller may cost more than the memory devices themselves.
Accordingly, it is desirable to provide a circuit for interfacing dynamic RAM memory devices to a single-chip microprocessor in a relatively low-cost and performance-effective manner satisfying all of the timing and event sequencing criteria for the refresh cycle of the RAM used.